Standard No.:	GB/T 43536.1-2023
English Name:	Three dimensional integrated circuit—Part 1：Terminologies and definitions
Chinese Name:	三维集成电路 第1部分：术语和定义
Chinese Classification:	L55    Microcircuit in general
Professional Classification:	GB    National Standard
Issued by:	SAMR; SAC
Issued on:	2023-12-28
Implemented on:	2024-4-1
Status:	valid
Language:	English
File Format:	PDF
Word Count:	9000 words
Price(USD):	270.0
Delivery:	via email in 1~3 business day

Three dimensional integrated circuit - Part 1 : Terminologies and definitions 1 Scope This document provides definitions and terms pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. This document is applicable to the fabrication and test of multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. 2 Normative reference There are no normative references in this document. 3 Terms and definitions 3.1 General The general terms listed below relate to the secondary integration method in vertical direction using integrated circuits fabricated on a horizontal surface of semiconductor. 3.1.1 interposer electrical interface that connects one socket or connection to another Note: The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection. 3.1.2 multichip interconnect technology technology that allows for the stacking of layers of basic electronic components which are connected using an interconnect fabric are as follows: Note 1: "Basic electronic components" are elementary circuit devices such as transistors, diodes, resistors, capacitors and inductors. Note 2: A special case of multichip interconnect technology is the interposer structures that may only contain interconnect layers, although in many cases other basic electronic components (in particular decoupling capacitors) maybe embedded into the interposer. 3.1.3 3-D bonding process that joins two die or wafer surfaces together multiple surfaces mechanically or electrically Example: Die-to-die, die-to-wafer, wafer-to-wafer 3.1.4 3-D stacking 3-D bonding operation that assumes electrical interconnects between two or more devices 3.1.5 3-D packaging 3-D integration of multiple dies using wire bonding, package-on-package stacking, or embedding in printed circuit boards 3.1.6 3-D wafer-level-packaging; 3-D WLP wafer level packaging technologies used for 3-D integration using Note: it is performed after wafer fabrication, which consists of flip-chip redistribution, redistribution interconnect, fan-in chip-size packaging, and fan-out reconstructed wafer chip-scale packaging. 3.1.7 redistribution layer; RDL extra metal layer on a chip that makes the I/O pads of an integrated circuit available in other locations 3.1.8 system in package; SIP integration of multiple dies, packages, or mixture of them as system in a package 3.1.9 3-D stacked integrated circuit integrated circuits of multiple dies using 3-D approach using direct interconnects without wire bonding Note: The 3-D stack uses a sequence of alternating front-end (devices) and back-end (interconnect) layers. 3.1.10 3-D integrated circuit; 3-D IC integrated circuit using 3-D approach through direct stacking of active devices Note: Interconnects are on the local on-chip interconnect levels. The 3-D stack is characterized by a stack of front-end devices, combined with a common back-end interconnect stack. 3.2 Test method in 3D environment 3.2.1 package stack integrated circuit packaging method to combine vertically discrete logic and memory ball grid array(BGA) packages Note: Two or more packages are installed atop each other 3.2.2 package-on-package; POP package in which separate packages are enclosed vertically Note: Two or more packages are installed atop each other. 3.2.3 multi-chip-package; MCP package in which multiple packages are enclosed 3.2.4 die stack chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit 3.2.5 contacting die stack chip in which two or more layers of active electronic components are integrated and signals between multiple layers are transferred via physical and electrical contacts 3.2.6 bump stud of metal protruded on the surface of die to provide the physical and electrical contact 3.2.7 micro bump small size bump to make an electrical contact between two dies 3.2.8 flip chip die interconnecting with the baseplate via the bump under the die 3.2.9 through-silicon via; TSV vertical interconnect access passing completely through a silicon wafer or die Note: Examples of TSVs are shown in Figure 1. 3.2.10 power TSV TSV intended to deliver power from one layer to another layer of stacked silicon wafers or dies Note: Examples are shown in Figure 1. 3.2.11 single drop signal TSV TSV intended to deliver electric signals from one layer to another layer of stacked silicon wafers or dies Note: An example is shown in Figure 1. 3.2.12 multiple drop signal TSV TSV intended to deliver electric signals from one layer to multiple layers of stacked silicon wafers or dies Note: An example is shown in Figure 1. 3.2.13 inter-die jumper TSV bridging circuits between adjacent two layers of stacked dies, that is not connected to the output pin of the package 3.2.14 single drop signal pin TSV connecting the first die and to a pin of the package 3.2.15 multiple drop signal pin TSV connecting delivering a signal from a pin of the package to multiple layers of dies