Standard No.:	GB/T 46280.5-2025
English Name:	Specification for chiplet interconnection interface - Part 5: Physical layer technical requirements based on 2.5D package
Chinese Name:	芯粒互联接口规范　第5部分：基于2.5D封装的物理层技术要求
Chinese Classification:	L55    Microcircuit in general
Professional Classification:	GB    National Standard
Source Content Issued by:	SAMR; SAC
Issued on:	2025-8-19
Implemented on:	2026-3-1
Status:	to be valid
Target Language:	English
File Format:	PDF
Word Count:	20000 words
Translation Price(USD):	600.0
Delivery:	via email in 1~8 business day

GB/T 46280.5-2025 Specification for chiplet interconnection interface - Part 5: Physical layer technical requirements based on 2.5D package English, Anglais, Englisch, Inglés, えいご This is a draft translation for reference among interesting stakeholders. The finalized translation (passing thorugh draft translation, self-check, revision and varification) will be delivered upon being ordered. ICS31.200 CCSL55 National Standard of the People's Republic of China GB/T46280.5-2025 Specification for chiplet interconnection interface - Part 5: Physical layer technical requirements based on 2.5D package Released on August 19, 2025 Implementation on March 1, 2026 State Administration for Market Regulation, National Standardization Administration Contents Preface 1 Scope 2 Normative references 3 Terms and definitions 4 Abbreviations 5 Logical sublayer 5.1 Logical sublayer functions 5.2 Data distribution 5.3 Redundancy Repair 6 Electrical Sublayer 7 Sideband Path 8 Chiplet Physical Layer Interface Specification for chiplet interconnection interface - Part 5: Physical layer technical requirements based on 2.5D package 1 Scope This document specifies the physical layer technical requirements based on 2.5D packaging, including initialization and training process, physical layer electrical characteristics, redundant The system must meet the relevant technical requirements for control, interface physical layout and low power consumption control. This document applies to the design, manufacture and application of chiplet interconnect interfaces. 2 Normative references The contents of the following documents constitute essential provisions of this document through normative references. For dated references, only the version corresponding to that date applies to this document. For undated references, the latest version (including all amendments) applies to this document. GB/T46280.1 Chip Interconnect Interface Specification Part 1: General Principles GB/T46280.3 Chip Interconnect Interface Specification Part 3: Data Link Layer Technical Requirements 3 Terms and Definitions The terms and definitions defined in GB/T 40268.1 apply to this document. 4 Abbreviations The following abbreviations apply to this document. AC: Alternating Current BIST: Built-In Self-Test CDA: Clock and Data Alignment CDM: Charged Device Model CPIF: ChipletPHYInterface DC: Direct Current DDR: Double Data Rate EMI: Electromagnetic Interference ESD: Electrostatic Discharge (ESD) ICR: Insertion Loss to Crosstalk Ratio ICG: Integrated Clock Gating IO: Input/Output port LPC: Low Power Mode (LowPowerCommand) LSB: Least Significant Bit NRZ: Non-Return to Zero PHY: Physical layer PI: Power Integrity PRBS: Pseudo-Random Binary Sequence PSXT: Crosstalk power (PowerSumCrosstalk) RX: Receiver SDR: Single Data Rate TX: Transmitter UI: Unit Interval 5 Logical Sublayer 5.1 Logical Sublayer Functions In the chiplet interconnection interface architecture specified in GB/T 46280.1, the physical layer includes a logical sublayer. The functional features implemented by the logical sublayer include: — Data distribution; — Redundancy repair; — Scrambling and descrambling; — Initialization; — Training and calibration. 5.2 Data Distribution Data within each lane is distributed to individual I/O devices for transmission in blocks. Data within each block is transmitted in LSB- first order. The default number of bits per block is 8; other values are determined by negotiation. Currently, high-bandwidth access supports a block size of 10 bits. For example, with 38 valid I/O devices per lane, the data distribution for each I/O device is shown in Figure 1. Figure 1 IO data distribution diagram 5.3 Redundancy Repair To improve interconnect yield, a spare IO can be set up in each lane for redundancy repair. Redundancy repair is not performed on clock signals. 2.5D packaging should support redundancy repair capabilities. When the number of data I/O per lane is less than 48, one I/O should be used as a backup I/O; when the number of data I/O per lane is greater than or equal to 48, two I/O should be used as backup I/O. If an interconnect failure occurs between two chiplets, it should be marked as a failure and removed from the other interconnection. All signals in the direction of signal shifting should also be rearranged until they terminate at the backup signal. Signal shifting should be performed simultaneously at both the transmitting and receiving ends